An image sensor is a semiconductor device that converts an optical image into an electric signal. One such image sensor is the complementary metal oxide semiconductor (hereinafter, referring to a CMOS) image sensor. The CMOS image sensor includes a plurality of unit pixels fabricated through CMOS processes. Each of the unit pixels includes one photodiode and three or four MOS transistors for driving the unit pixel. The CMOS image sensor employs CMOS technology that uses a control circuit and a signal processing circuit as a peripheral circuit. The MOS transistors are formed based on the number of pixels, while the output data is successively detected through the use of the MOS transistors.
In fabricating these various kinds of image sensors, many attempts to increase photosensitivity have been made. One such attempt is a light integrating technology. For example, the CMOS image sensor includes a photodiode for sensing light and a CMOS logic circuit for processing the sensed light into an electric data signal. In order to increase photosensitivity, an attempt to increase a fill factor has been made. The fill factor is a ratio of a photodiode with respect to a total area of the image sensor.
FIG. 1, which has been reprinted from U.S. Published Application No. 2006/0186504A1 to Bae et al., the entirety of which is hereby incorporated by reference, is a circuit diagram showing a unit pixel of a CMOS image sensor, in which the unit pixel includes four transistors. As shown, the unit pixel of the image sensor includes a photodiode PD constructing a PNP junction, a PNPN junction or the like, a transfer transistor TX, a floating diffusion node FD, a reset transistor RX, a drive transistor DX, and a select transistor SX. The photodiode PD receives light from an object to generate corresponding electron-hole pairs, i.e., photogenerated charges. The transfer transistor TX transfers the photogenerated charges accumulated at the photodiode PD to the floating diffusion node FD when the transfer transistor TX is turned on. When the transfer transistor TX is turned on, the floating diffusion node FD receives the photogenerated charges transferred from the transfer transistor TX. The reset transistor RX resets a voltage of the floating diffusion node FD to a power voltage VDD level in response to a reset signal. An amount of turning on a gate of the drive transistor DX is varied with an electric signal corresponding to the photogenerated charges transferred from the floating diffusion node FD, so that the drive transistor DX outputs the electric signal in proportion to the amount of the photogenerated charges. The select transistor SX, which is turned on based on a select signal, outputs a signal of the unit pixel through the drive transistor DX.
As shown in FIG. 1, a reference numeral LX represents a load transistor. The floating diffusion node FD has a predetermined capacitance Cfd.
The operation principle of obtaining an output voltage VOUT from the unit pixel of FIG. 1 is described below.
First, the transfer transistor TX, the reset transistor RX, and the select transistor SX are turned off. At this time, the photodiode PD is in a fully depleted state. A light integration is started to collect the photogenerated charges at the photodiode PD.
After an appropriate light integration time, the voltage of the floating diffusion node FD is reset as the reset transistor RX is turned on. Then, the select transistor SX is turned on. At this time, a first output voltage V1 of the unit pixel at a reset operation is measured. The measured value means a DC level shift of the voltage of the floating diffusion node FD.
Then, the transfer transistor TX is turned on so that all the photogenerated charges at the photodiode PD are transferred to the floating diffusion node FD. Then, the transfer transistor TX is turned off. At this time, a second output voltage V2 due to the charges transferred to the floating diffusion node FD is measured.
The output voltage VOUT, which is a transfer result of the photogenerated charges, is obtained from the difference between the first output voltage V1 and the second output voltage V2. That is, the output voltage VOUT is purely a signal voltage except for a noise. This method is referred to as a correlated double sampling (CDS).
The transfer transistor TX transfers the photogenerated charges to the floating diffusion node FD. Meanwhile, the transfer transistor TX has several problems when a transfer control signal applied to a gate of a transfer transistor is dropped from a logic level ‘HIGH’ to a logic level ‘LOW’, that is, when it changes from a turned-on state to a turned-off state. When a falling time of the transfer control signal is short, a charge injection to the floating diffusion node FD can occur. The charge injection occurs differently in pixels. Therefore, when seen from the outside, it appears that noise occurs. This phenomenon is called partition noise. Since the partition noise is considered as noise on a screen, it acts as a factor that degrades the performance of the image sensor.
FIG. 2 portrays a prior art CMOS image sensor 10 having a conventional buffer 12 and pixel array 14. The pixel array 14 has “m” number of rows and “n” number of columns of unit pixels P, though only two rows of pixels are shown for ease of illustration. The buffer passes row control signals such as TX, RX and SX from a row control circuit to the pixel array 14. For ease of illustration, FIG. 2 shows the provision of transfer control signal TX0 and TX1 from drivers Drv0 and Drv1, respectively. The conventional buffer 12 includes a plurality of inverters for passing the transfer control signals TX0 to TXm to the rows of pixels. If no slew rate control is provided within buffer 12 for controlling the slope of the transition of the control signal (e.g., TX) from high to low, a wide distribution of slopes for the control signal as seen at individual pixels (i.e., TXm[0] to TXm[n]) can occur due to the parasitic wire resistances R and parasitic capacitances C, as shown in FIG. 3A. In particular, FIG. 3A illustrates simulation results when no slew rate control is employed in a buffer 12. As can be seen from slope lines 22, there is a wide distribution in the slopes of the down transition of the control signal TX[0] to TX[n], which results in different charge injection at individual pixels and clock-feed through, which manifests as partition noise. When slew rate control is employed within buffer 12, a narrow distribution in the control signal down slopes is realized, as shown by slope lines 24 in FIG. 3B.
Bae et al. describe various slew rate control implementations for buffer 12 that can improve the partition noise of the CMOS image sensor. Specifically, these embodiments increase the falling time of the transfer control signal applied to the gate of the transfer transistor. In a first embodiment, shown in FIG. 4, the falling time of the control signal is increased by reducing a W/L ratio of an NMOS transistor N1 of the CMOS inverter of buffer 12. Specifically, a resistance through the transistor N1 can be increased, i.e., a current is decreased, by increasing the length L or decreasing the width W, thereby increasing the falling time of the transfer control signal. Meanwhile, the width W of the gate electrode is related to the design rule of the device. Accordingly, a method of reducing the W/L ratio without modifying the design rule is to increase the length L of the gate electrode when the width W of the NMOS transistor is fixed.
A second approach to slew rate control disclosed in Bae et al. is shown in FIG. 5 and involves serially connecting a number of NMOS transistors (e.g., N1 to N4) to obtain a desired falling time.
An alternative approach to slew rate control is disclosed in U.S. Patent Publication No. 2007/0001101 A1, filed by Raj Sundararaman et al., the entirety of which is hereby incorporated by reference. Sundararaman et al. uses bias control to control the slew rate of the control signal for reducing partition noise of a CMOS image sensor.
Another important problem that arises in the use of CMOS image sensors is the coupling of control signals between adjacent rows due to parasitic coupling capacitances between adjacent rows (labeled Cc in FIG. 2). The prior art discussed above addresses the partition noise problem but does not address coupling noise and other issues attributable to these parasitic capacitances. In fact, the slew rate control approaches of the prior art can exacerbate the problems associated with coupling of adjacent signals between rows. For example, in some prior art approaches, the NMOS transistors of the buffer 12 have high turn on resistances in order to provide the desired slew rate. An unselected row should be pulled low at its static state. However, due to the high NMOS resistances in the drivers, the control signals for pulling the unselected row are weak and adjacent signals from an active row are easily coupled to the inactive row. This results in low power efficiency due to leakage current or even improper operation of the CMOS image sensor.
A driver for CMOS sensor that reduces partition noise and simultaneously minimizes the negative effects of capacitance coupling between adjacent rows is desired.